Wide Dynamic Range Capture Based on Mantissa-Exponent Representation

WDR Sensor - Block View

WDR Sensor - Block View

The system can capture WDR scenes and stream the captured data to the LDR display in real-time mode @60ffps
The system includes an image sensor, FPGA, and display (monitor).
The image sensor is designed to perform up to 8 conditional resets for each pixel during the integration time to avoid saturation at the end of the frame time. 
To implement this logic and to establish parallel access and conditional resets to 8 pixels, components were designed and integrated together. These components included: 9-bit Row Decoder, Single bit ADC (latched comparator), parallel 256 to 8 bits multiplexer, parallel 9-bit Reset Logic unit, parallel 9 to 256 bits multiplexer, Row Driver, and multiple access low noise pixel. 

WDR Sensor Testing System
Sensor Output Results

Conclusions & Further work

•Presented WDR sensor, Interface board, HDL driver

•The presented pipeline is able to sample and generate up to 8 AR

•Achieved 96 dB of Linear Dynamic range with a high frame rate

Low memory is required to generate WDR data

•New pixel must be designed to reduce leakage current (based on PD)

•The pipeline can be improved to access reset logic and pixel scan process

•Internal ADC must be considered to take full advantage of CMOS Opto-process